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How to calculate a memory of a specific size
I would like to design a 4kb memory.
The size of a memory is equal to 2^m words or 2^m*n bits, m for address lines n for data lines.
In verilog we can write
reg [WordSize-1:0] Mem [0:Address_width];
...
B. George
Votes: 0
Answers: 1
Verilog simulator don't execute command
I have written a program to describe the multiplexer in Figure 4.26. When I run the test bench some commands wasn't executed. I don't know where my code is wrong, can someone explain it to me
This is ...
huutrang93
Votes: 0
Answers: 1
Why does this for loop containing a delay not run to completion?
I have two test benches:
// test_a.v
module test_a;
initial
begin
for (int i = 0; i < 128; i++) begin
$display("hello");
#10;
end
end
e...
dipea
Votes: 0
Answers: 1
modelsim simulation time cycles appear to be different than test_bench
i have a testbench which states at the top:
'timescale 1 ns/ 1 ps
a clock which is defined as:
code in testbench
always begin
#5 sys_clk = ~sys_clk;
#20 clk_in = ~clk_in;
#8 clk_acq = ~clk_a...
Dan
Votes: 0
Answers: 1